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It's a dual-issue superscalar machine with an stage integer pipeline, instruction reordering, speculative execution, and optional symmetric multiprocessing. AudiobookStand Discount Audiobooks on Disc.
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Way better widgets and the fact that you can have widgets!! Nevertheless, it easily beats Intel's integrated GPUs. 7 inch android phones how to unlock No longer satisfied with existing strongholds in PCs and servers, this year Intel has revived the x86 as a standalone embedded processor and has introduced the first highly integrated xbased SoCs. Yeah but pregnancy test and mosquito shield will happen, right? Sparc64 X multichip interconnects.
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Apple cant even help me. Block diagram of the Godson-3's GS processor core.
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Godson GSV block diagram. Jul 3rd, at 8: Feb 27th, at 4: Apple iPhone 6 Space Gray Unboxing. Nov 1st, at 5: MIPS P six-core coherent cluster. How long did the research take?
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04.03.2018 - No I just googled all that to try to see if his points were credible. Now they will return the money to all the people who were involved in the Power Clouds project? Learn more about Amazon Prime. The core chip, which has been sampling for nearly a year, resembles Cavium's future core ThunderX2 in many respects but falls short of the best x86 server chips. Then I ask the person promoting it, Why would I buy it for from you when I can get the same product for 26 dollars on Ebay.
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28.02.2018 - The multicore chips with dual ARM cores can independently run high-level application code and low-level control code. Share your thoughts with other customers. This is pretty annoying. Wait for your asnwer as soon as possible, before i take other providences.
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24.01.2018 - Some future QorIQ chips will have at least 16 cores. Like the insurance policies, the lower tiers Bronze and Silver cost less but offer fewer benefits than the higher tiers Gold and Platinum. A binary compensation structure places an affiliate at the top of a binary team, split into two sides left and right: She entered the field in as an analyst for Dataquest, covering minicomputers and printers. Where else can you go and start a traditional business for that little money and have the opportunity for sharing the product and all of its great benefits and get paid. And the most of the projects were not grounded on realistic base:. Amazon Fire TV Stick video The products department is split into the following ten departments, each with a number of sub-departments.
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Whereas the powerful Sparc M7 is designed for scale-up computing, Sonoma is designed for scale-out applications. Yet it retains the bigger processor's unique features, such as hardware accelerators for the company's database software and application-data integrity checking.
Other features for reliability, availability, and serviceability RAS made the cut, too. At the recent Hot Chips conference, Oracle presented Sonoma as a junior version of the Sparc M7 that costs less money, consumes less power, and requires less board space.
Die plot of Oracle's Sparc Sonoma processor. Sonoma versus Sparc T It includes an always-on sound detector that can listen and respond to predefined voice triggers while drawing a mere microamps.
DPAA2 is a major revision of the data plane that is more powerful, more flexible, and more programmable than the company's previous designs. It was inspired by Nokia's Open Event Machine, a model for nonblocking data-plane processing that supersedes conventional thread-based models in multicore processors.
Layer 2 Ethernet switch. These new chips are designed mainly for intelligent network interface cards NICs and edge routers, and they are also useful for industrial and aerospace applications.
Freescale also made two important roadmap announcements: Some of those 16nm PowerPC chips will be shrinks of existing 28nm T-series designs; others will be fresh designs. The CN72xx and CN73xx midrange products are scheduled to begin sampling in July and start volume production in 4Q15, the company says.
The fast ramp from sampling to production is possible because Cavium has already delivered four other series of lower - and higher-end Octeon III chips using the same GlobalFoundries 28nm process.
Cavium's Octeon III family. Implemented as synthesizable intellectual property IP, the new Ice-Grain subsystem will work with any interconnect and can bring sophisticated energy-saving technology to any SoC design.
Similar technology is proprietary and appears only in some advanced SoCs designed by top-tier chip vendors. Ice-Grain not to be confused with "in-circuit emulation" is a hierarchical control subsystem that manages power, clock, and voltage domains.
It enables chip architects to divide their designs into many more individually controllable domains than are practical using conventional techniques. By having more domains, the chip can power only those circuits it needs at any given moment, thereby reducing both active power and static leakage.
Ice-Grain integration with SonicsGN. Power-saving techniques ranked by transition latency. Arteris FlexNoC Gets Physical Licensable Network-on-a-Chip Eases Timing Closure Hoping to reduce the number of chip designers furloughed to funny farms, Arteris has introduced a new version of its licensable network-on-a-chip NoC that tackles one of the industry's most maddening problems: By adding some physical awareness and layout automation to the early phases of the design process, FlexNoC Physical ensures that signals can traverse the chip's interconnects within the design's timing parameters.
As a leading vendor of NoC intellectual property IP with more than 60 licensees, Arteris has industrywide visibility into the problem. FlexNoC Physical is the company's response to customer demand for a timing solution that precedes logic synthesis and physical layout.
Arteris FlexNoC block diagram. FlexNoC versus a conventional crossbar. The chip is sampling now in 28nm technology and scheduled for volume production in 3Q Omitting some cellular-specific features reduces the chip's cost and power consumption.
We suspect the 66AK2L06 is actually the same die, which would enable TI to salvage some base-station chips whose wireless hardware fails to pass muster. In June, the company plans to sample a new processor family designed for advanced driver-assistance systems ADAS.
The first chip is the S32V, which combines real-time computer vision with intelligent image analysis, enabling such functions as autonomous emergency braking, lane-departure correction, road-sign recognition, and adaptive cruise control.
Two Cognivue Apex cores each clocking at MHz handle the computer-vision processing, aided by an image signal processor. A Freescale cryptography engine enables secure communications with other system components and the outside world.
Freescale S32V block diagram. Cognivue Apex block diagram. The eyes see, but the brain interprets and reacts. Thus, processing power is as vital to computer vision as image capture. To augment those back-end functions, Ceva has introduced a new licensable DSP core optimized for vision processing.
It quadruples the number of multiply-accumulate MAC units, quadruples the width of VLIW operations, adds bit floating-point units and vector operations, and doubles the number of scalar units.
Intended for Gbps data-plane networking and network-function virtualization, the Tile-Mx significantly raises the bar for manycore ARM designs. EZchip Tile-Mx block diagram. A SkyMesh quad-core tile.
Comparison of manycore processors for networking: And AMD hopes Carrizo's gravitational attraction will be so irresistible that customers will never achieve escape velocity for a return trip to Planet Intel.
Carrizo succeeds the Kaveri processors that appeared last year. A related family, Carrizo-L, cuts costs and power further by omitting several features; it succeeds the Beema processors also introduced last year.
Both new processors will appear mainly in low-cost notebook PCs, small desktops, and convertible tablet notebooks. AMD Carrizo die photo. These awards span several categories: We have presented them in Microprocessor Report for many years.
This year, we are adding two new categories to recognize chips that are not processors: The new categories reflect our expanded coverage of these areas in our sister publications Mobile Chip Report and Networking Report.
To choose each winner, The Linley Group's team of technology analysts gathered to discuss the merits of the leading products that entered production or, in the case of IP, production RTL in This guideline eliminates "paper" products and allows us to evaluate delivered capabilities, not promises.
We also considered only merchant offerings e. Our analyst team is deeply familiar with all the leading products, having written about them over the course of the past year.
We selected the winners on the basis of their performance, power, features, and cost for their target applications. Newly disclosed scores show Power8 beating Intel's most powerful server processor, the core Xeon Ev3 Haswell-EP, on important benchmark tests.
Both processors deliver outstanding performance on the SPEC CPU benchmarks, but IBM's huge advantages in multithreading and memory bandwidth favor Power8 when running larger test suites that more closely reflect real-world enterprise applications.
Overall, the results show that IBM offers a viable high-end alternative to Intel's market-leading products. Equally important to Big Blue, Power8's performance is energizing the OpenPower Foundation, an IBM-led alliance that rallies other companies to create a larger hardware and software ecosystem around the processor.
IBM is offering Power8 chips to system builders in the merchant semiconductor market and is even licensing the architecture to other processor vendors. IBM Power8 processors for the merchant market.
Although the dollar amount was undisclosed, it will strengthen the startup's position versus established rivals like Sonics and Arteris. NetSpeed also faces growing competition from ARM, whose licensable cache-coherent interconnects are becoming more sophisticated and are encroaching on some territory the NoC vendors have staked out.
The growing complexity of SoC designs is creating more opportunities for licensable NoCs. NetSpeed's NocStudio configuration tool. Orion versus Amba AXI. Two Gemini NoC implementations.
All are compatible with the bit ARMv8 architecture. Those single - and dual-core chips are highly optimized for packet processing and communications. By contrast, Helix chips have two, four, or eight bit CPUs, and we believe they have much of the same packet acceleration as the PacketPro Mamba and Diamondback processors.
Block diagram of AppliedMicro's Helix 2 embedded processor. Feature comparison of AppliedMicro's Helix embedded processors. Despite their maximum target clock frequency of 1.
Applications include integrated-services branch routers, security appliances, industrial controllers, and edge devices that implement software-defined networking SDN and network-function virtualization NFV.
It is the most powerful implementation of the ARCv2 instruction-set architecture. Targets include Wi-Fi routers, Internet gateways, digital TVs, smart appliances, and advanced driver-assistance systems.
Consequently, it can run a virtual-memory operating system, such as full versions of Linux. The bit synthesizable CPU also supports dual - and quad-core clusters with cache-coherent symmetric multiprocessing SMP.
Yet it retains the user configurability, low power consumption, and small size of its ARC predecessors. Simulations indicate the HS38 will deliver a maximum worst-case clock frequency of 1. The typical clock frequency in that process is 2.
KeyStone Targets Industrial Apps [Brief Item] Texas Instruments is sampling four KeyStone II processors it originally announced two years ago and is extending their temperature range for industrial and military-aerospace applications.
Although they are intended mainly for networked industrial applications, their switched Ethernet ports and optional DSP also suit them to enterprise gateways. General sampling began in September, and production is scheduled to start by the end of this year.
In fact, this is the first processor we've seen that uses Micron's stacked-memory cubes. And the core counts are doubling with each generation. Sparc64 XIfx die photo with overlay.
Block diagram of Sparc64 XIfx core groups. The next-generation Sparc M7 weighs in with more than 10 billion transistors on a die we estimate at about mm 2. Each of its 32 CPU cores can simultaneously execute eight threads, and the chip has more than 70MB of cache.
What to do with this monster? Run Oracle's database software, of course. Since Oracle acquired Sun Microsystems in and took over SPARC development, it has executed a surprisingly aggressive roadmap that has new processors coming out every year.
Because Oracle is virtually the only customer for these processors, the architects can tune them for the company's famous enterprise software. Oracle Sparc M7 die photo. Sparc M7 performance versus Sparc M6.
The new chips began sampling in 1Q14 and are scheduled for production in 4Q Block diagram of Broadcom's BCM Key parameters for Broadcom's BCMx5 base-station processors.
Like their forebears, the new processors target a broad range of embedded applications, but they focus on real-time industrial communications, test-and-measurement instruments, barcode scanners, portable data terminals, medical devices, and GPS navigation.
TI's new Sitara AMx series: Those are the code-names for six new Embedded G-Series SoCs that will go talon to talon with Intel's Atom and other high-performance embedded processors. Although AMD is optimistically pitching the new dual - and quad-core chips for data-center switches and network-security appliances, their main markets are PC-like embedded systems: Such systems commonly employ x86 embedded processors derived from PC processors and usually run Windows or Linux.
The new chips are in production now, and their clock speeds of 1. Its escort is the Armada, a single-core model based on the same die. Both processors target small-business, enterprise, and carrier-class communications equipment, such as Marvell Armada block diagram.
Example Wi-Fi access point using the Armada and other Marvell chips. Comparison of Marvell's Armada, , , and Mindspeed, which originated as a Conexant spinoff in, has now been chopped into three pieces.
Macom is retaining Mindspeed's extensive analog portfolio and Comcerto voice-over-IP VoIP processors but is selling the Comcerto gateway processors to Freescale for an undisclosed sum.
The T is a quad-core eight-thread processor optimized for midrange communications infrastructure, and the others are single - and dual-core processors optimized for low-end communications and general embedded applications.
These eagerly awaited 28nm chips fill several gaps in the QorIQ T-series, finally superseding some popular but aging P-series processors manufactured in 45nm technology. QorIQ T block diagram.
The new XLP series comprises three basic models with four, six, or eight CPU cores and two package options, for a total of six distinct products. The faster network interfaces launch these midrange products into the same stratosphere as previous-generation high-end processors.
Previously, only high-end communications processors supported 40GbE interfaces. Doubling the number of CPU cores and threads will help these muscular devices handle the faster packet flows.
Block diagram of Broadcom XLP An XLP wireless base station. Small-cell LTE base station. Freescale's QorIQ Qonverge family. Key parameters for Qonverge B, B, and B processors. Freescale's Qonverge B versus two competitors: Microchip designed the PIC32MZ family for high-end controller applications, such as vehicle dashboard systems, building environmental controls, and consumer-appliance control modules.
Our analyst team is deeply familiar with all the leading processor products, having written about them for Microprocessor Report over the course of the past year.
Intel C family Best Processor Technology: For now, though, embedded processors are athletes in the prime of life, achieving record-breaking performance. Cavium's core Octeon III, another 28nm giant, has yet to sample.
Two additional trends apparent in were further movement toward the ARM architecture and bit processing. Tilera's Tile-Gx posted the highest single-socket CoreMark score. Although the processor giant is saying little about the deal, it has acquired Mindspeed's inventories and intends to fulfill the product roadmap, including the new Transcede T and T base-station processors announced last year.
Before Intel's December 16 offer, Mindspeed's wireless business looked precarious. Although Mindspeed's analog technology was a desirable acquisition target, Macom had no interest in the base-station processors.
Had Mindspeed not found a buyer for those processors, Macom would have discontinued them. SEC filings suggest that Mindspeed was already negotiating their sale to Intel before Macom tendered its bid for the rest of the company.
Future members of the IPQ family will target other network-edge devices, such as small-business access points and small-cell base stations. Although these markets are already crowded with major competitors, Qualcomm hopes to succeed by applying its experience in related fields, such as smartphones, cellular base stations, Wi-Fi access points, and Ethernet switching.
The IPQ is the primary product; the other chip is a slightly slower and lower-cost subset. Scheduled for production in 1Q14, this first xCore-XA device will be followed by additional models having slightly different features.
Although other xCore chips can handle both tasks, ARM compatibility lets developers use their existing code for the higher-level software while running optimized control code on the proprietary core.
Simulations indicate it will reach clock frequencies of up to 1. But clock speed isn't the only selling point: ARC HS cores also improve power efficiency, silicon area, code density, integer throughput, floating-point performance, and real-time trace features.
The other new CPU, the ARC HS36, is intended primarily for higher-end mobile consumer products, such as digital cameras and tablets, as well as for digital TVs, set-top boxes, automobile infotainment systems, and the "Internet of Things" noncomputer devices.
ARC HS block diagram. ARC HS instruction pipeline. The P is the first member of the Series5 Warrior family and is designed for consumer electronics, smartphones, tablets, and other high-performance embedded systems.
It's a licensable and synthesizable bit CPU core with a stage instruction pipeline, four-issue superscalar execution, instruction reordering, improved branch prediction, extended memory addressing, and hardware virtualization.
Its bit dual-issue SIMD units can handle single - and double-precision floating-point operations as well as integer data types. By pairing some operations, the P can effectively issue up to eight instructions per clock cycle.
MIPS P block diagram. MIPS P load pipeline. MIPS P six-core coherent cluster. Comparison of high-performance bit CPU cores. IDC estimates that compact-digicam sales will plunge to 80 million units this year from million in In comparison, The Linley Group forecasts million smartphones will sell this year.
Now, a major sensor supplier is promising higher quality and greater light sensitivity with smaller pixels. Comparison using Macbeth color chart. The classic Bayer color-filter array versus four alternatives.
Intel Tests Code Compression [Brief Item] Intel Labs has demonstrated a compile-time code-compression technology in which a processor unpacks the compressed program at run time. The goal is to cut silicon costs by reducing the amount of on-chip memory.
Although Intel calls the technology "direct compressed execution," the compressed program is actually decompressed on the fly before execution. It differs from other code-compression techniques such as ARM's Thumb that replace bit instructions with bit opcodes.
Instead of using a modified instruction set, programmers write, compile, and link their code as usual, then employ a special utility to compress the binary file. Slated for production this fall, these multichip MCUs are intended mainly for high-end audio gear, automobile infotainment systems, factory robots, and other industrial applications.
Moreover, the CPUs support hardware multithreading with up to eight threads per core. These threads which XMOS calls "logical cores" share equal time by executing in a deterministic round-robin fashion, switching contexts on every clock cycle.
Three families of XMOS bit microcontrollers. Sporting 20 CPU cores running at 2. Moreover, a special interchip interface can unite a maximum of eight processors in a cache-coherent cluster whose total throughput is 1.
With its cryptographic engines, regular-expression reg-ex acceleration, RAID acceleration, packet accelerators, and compression engines, it can manage routing, switching, security processing, load balancing, and cloud storage.
New virtualization features open doors into data-center processing. Broadcom XLP block diagram. MIPS64 Release 5 virtualization. Broadcom's Interchip Coherency Interface. Comparison of high-end communications processors: They also retain the integrated Gigabit Ethernet switches that set this family apart from other embedded processors.
Their primary markets are enterprise access points and small-business Wi-Fi routers. Both new StrataGX processors have dual 1. The new high-end chip in the family is the BCM, intended mainly for enterprise Wi-Fi access points.
When paired with Broadcom's Ethernet switch chips, it can also handle control-plane processing and cryptography acceleration. Key parameters for Broadcom's StrataGX processors.
Designed for low-cost storage control, media servers, and light-duty networking, the surpasses other Armada series chips and measures up to processors in the higher-end Armada XP family. With the S family code-named Centerton, the company has extended Atom into servers as well.
The S and S processors run at 1. They began production in 1Q Although the informal "law" has brought the industry vast fame and riches, complying with its rigid demands and relentless schedule is becoming enormously expensive.
It is also forcing researchers to experiment with increasingly extreme technologies, in turn forcing chip designers to face a more confusing array of choices. The growing costs and complexity of chip manufacturing were evident at two recent foundry events in Silicon Valley.
The roadmaps unveiled at these events are vital information, because almost all chip companies have committed to a fabless or "fab-lite" business model that outsources manufacturing.
Relative costs of new process technologies. Comparison of four GlobalFoundries process technologies. To support these claims, the company released 17 world-record benchmark results.
It also achieves top scores on several database, middleware, and system-level benchmarks appropriate for Oracle's enterprise-server business. Sparc T5 die photo with overlay.
Foremost were new base-station processors from Broadcom and Mindspeed. Mindspeed announced two second-generation dual-mode designs, the Transcede T and T New base-station processors from Broadcom and Mindspeed.
This monolithic design is a unique achievement of manycore integration in 40nm CMOS technology. Each CPU has a maximum clock frequency of 1. The mesh arranges the CPUs in an eight-by-nine tiled matrix that provides more than terabits per second of aggregate bandwidth.
The company has announced three new chips that will challenge the dominant market leader, Cavium's Nitrox family. Freescale's new C29x chips join additional newcomers: Intel's DHfamily "Cave Creek" chips, which were introduced last quarter.
Why is Freescale entering this market now? For one thing, the company expects demand for public-key cryptography performance to rise as the industry switches from the widely used 1,bit keys to the safer 2,bit keys recommended by the U.
Also, the dearth of competition has convinced Freescale that there's room for a lower-priced product. Example system design based on Freescale's C29x. High-performance crypto coprocessors from Freescale, Cavium, and Intel.
For its achievements in replacing conventional clock-signal trees with a resonant clock mesh and easing the design of high-performance chips, Cyclos nets The Linley Group's Analysts' Choice Award for the best new microprocessor-related technology of High-speed processors impose many design challenges, not the least being the rising power consumption of complex clock trees.
Essential for uniform timing, these circuits have numerous branches that carry clock signals to every nook and cranny of a chip. But as processors get faster and more complex, clock trees struggle to keep up and can account for one-third of the chip's power consumption.
The leading alternative, especially for processors exceeding 2. Cyclos reduces power consumption in clock meshes by connecting them with integrated inductors to form resonant LC oscillators. Lawyers dream of rewriting landmark court rulings.
Engineers dream of redesigning microprocessor architectures. But such opportunities are so rare that few practitioners ever get a chance to make such fundamental changes.
Starting in, some lucky engineers at ARM got that chance. Nevertheless, they got a once-in-a-lifetime opportunity to overhaul an architecture that remains quite serviceable but has some crufty features that impair performance.
Since we first covered ARMv8 last year, the company has released much more documentation, allowing a more thorough analysis. Although ARM's tardiness in moving to 64 bits has undoubtedly cost the company some opportunities, ARMv8 is an extensive revision, and the delay has allowed ARM's architects to learn from other companies' experience and mistakes.
ARMv8's privileged-execution model in AArch ARMv8's bit memory map. ARMv8's optional cryptography instructions. These tiny chips squash the list price of bit MCUs to as little as 39 cents each in 10,unit volumes.
It seems impossible that a bit MCU could cost so little and function with only eight pins. But then, no other processors can match the credentials of Texas Instruments' new KeyStone chips: Just about the only thing TI left out is cellular-baseband acceleration, distinguishing these chips from the company's KeyStone II base-station processors.
Broadcom is also sampling six newly announced processors: Note that some of these chips have the same names as previous XLP chips fabricated in 40nm technology.
All the new XLP II processors are single - or dual-core chips with one to eight threads and a target clock frequency of 2. But at 12MHz, it uses only 2. The key to prolonging battery life is to sleep as much as possible, then quickly wake up and do a brief burst of work before slumbering again.
In deep sleep, only the real-time clock RTC remains awake. It can supervise simple tasks without disturbing the CPU, because the peripherals have some autonomy.
Whereas Fujitsu's tenth-generation Sparc64 X design emphasizes per-thread throughput, Oracle's Sparc T5 excels at multichip scaling. This article focuses on Fujitsu's processor, for which more information is available.
Oracle was more reticent but did reveal some new features. These companies are the only remaining developers of high-performance SPARC processors and are their own biggest customers.
Fujitsu Sparc64 X die photo. Sparc64 X instruction pipeline. Sparc64 X multichip interconnects. Oracle's Sparc T5 multichip configuration. DesignArt's 4G base-station processors surpass Qualcomm's existing 3G femtocell products by offering much higher data rates and user capacities.
In addition, Qualcomm gains DesignArt's important wireless-backhaul technology and a respected engineering team. DesignArt is an Israeli fabless semiconductor company founded in Well, not quite, but it seems that way.
The latest chips to come within ARM's reach are Freescale's market-leading QorIQ communications processors, which are also the best-selling flag bearers of the Power Architecture. Freescale's Layerscape chip-level architecture.
Freescale Targets Smaller Cells [Brief Item] Integrated processors for wireless base stations continue to proliferate. These chips are pin compatible and the first Freescale products to sample in 28nm HPM technology.
Samples are due in 3Q12, with production scheduled for 2H First, China wants to standardize on a single instruction-set architecture for all future government-sponsored projects. These events lead me to suggest that the Chinese government or one of its semiprivate entities should acquire MIPS.
But when judged purely as a business and technology proposition, the deal makes more sense than many other scenarios. The latest additions are the quad-core P, which has twice as many CPU cores as previous P5-series chips, and the dual-core P, which improves on the existing P Both new processors also add more Ethernet controllers and raise the maximum clock speed of their Power e CPU cores to 2.
Having twice as many CPUs as the existing P, the P bolsters Freescale's offerings for control processing and will improve the company's competitive stance against Intel's new Ivy Bridge embedded processors.
Freescale QorIQ P block diagram. Parallelism for the Masses Intel's "River Trail" Adds Easy Parallel Processing to JavaScript Unlocking the parallelism of multicore processors has vexed the industry since the first such chips burst onto the scene in With a project code-named River Trail, Intel Labs is taking a refreshingly different approach.
Intel's proposed JavaScript extension is so abstract that programmers need know nothing about the system's hardware. At run time, the web browser's modified JavaScript engine automatically discovers and adapts to any parallel-processing resources available.
It can use the CPU's vector-arithmetic instructions, multiple CPU cores per chip, multiple threads per core, and multiple processors per system. The latest experimental version can even assign tasks to some integrated GPUs.
River Trail demo screen. Parallelism with River Trail. One purpose for dual-band operation is to support the future Another dual-band scenario is a single client transmitting 2.
The multicore chips with dual ARM cores can independently run high-level application code and low-level control code. One multicore Vybrid chip can replace at least two separate chips while keeping software development on a common bit ARM platform.
But the new chip aims significantly higher, and system designers can link multiple chips together to build even larger base stations. TI's KeyStone integrated base-station processors.
Chips eliminated from a conventional base station design. Key parameters of integrated base-station processors: By skipping the tedious steps of translating marketing concepts into gate-level logic, the new PowerSynth tool makes design engineers obsolete and allows anyone to be a CPU architect.
PowerSynth uses patented artificial-intelligence algorithms to generate production-ready logic from common PowerPoint drawing objects. Typical SoC blockhead diagram.
The B will bring CPU-DSP integration to large cellular base stations and is among the company's first chips manufactured in 28nm technology. Two contrasting designs for LTE macrocell base stations.
Key features of high-performance DSP cores: Freescale's QorIQ Qonverge family: An instruction set composed almost entirely of bit instructions. Are we in the disco days of the s? Nope, it's, and ARM is introducing a new bit CPU core that plumbs the depths of simplicity and low power consumption.
Even by RISC standards, a bit design can't get much simpler than this. Although it uses less power than a Cortex-M0, it wears a plus sign instead of a minus because it adds features.
The T is a highly integrated design with 12 CPU cores arranged in three quad-core clusters. By contrast, the biggest existing QorIQ design is the eight-core P Moreover, the T debuts Freescale's new bit Power e dual-threaded CPU core, whereas the P uses the bit Power emc single-threaded core.
The new CPU, apart from other features, ensures that the T will be a much more powerful processor. QorIQ T multithreading performance. Power e CPU cluster. Wireless Wants to Wallop Wires Emerging The draft specification is close enough to final that companies like Broadcom, Quantenna, and Redpine Signals are already introducing the first The big news about We've heard such claims before, but Comparison of antenna technologies: Data rates for Broadcom's BCM43xx transceiver chips for Nevertheless, the design win helps establish Armada as an up-and-coming product line for smart TVs, Blu-ray players, and advanced set-top boxes.
Our pick for Although engineers have been working for years on the concept of three-dimensional ICs, new developments in virtually guarantee that stacked-memory devices are finally on their way to commercial production in the near future.
Other technologies we considered for this award are noteworthy, too. We nominated four candidates from Intel: The first commercial devices will stack four DRAM die connected using through-silicon vias.
This asymmetric or heterogeneous multicore design combines the high performance of application processors with the real-time response of microcontrollers. The new chips can be considered application-class SoCs with real-time credentials or bit MCUs with application aspirations.
By contrast, ARM's Big. Little strategy integrates a Cortex-A15 "big" core with a Cortex-A7 "little" core and is designed to save power in mobile application processors. Freescale AeMPU simplified block diagram.
In fact, they probably are derived from last year's smartphone processors. And if Xilinx prepares to send a man to Mars, Altera will start building rockets. The two leading FPGA vendors are that competitive.
So it's no surprise that Altera has announced its answer to Xilinx's Zynq chips, which are customizable SoCs that integrate ARM Cortex-A9 cores and hard peripherals with programmable logic.
But Altera isn't a copycat, because both companies are hearing the same pleas from customers and are building on experience with similar products introduced more than a decade ago. To keep the heat on rivals like Cavium, Freescale, and Intel, NetLogic must keep its transition to a new product line and 28nm technology on schedule.
NetLogic's Interchip Coherency Interface supports four - and eight-chip memory-coherent clusters. The STM32 F4 series includes four basic designs with various integrated peripherals. Prototype chips are promising enough that commercial products may be only a few years away.
If Intel can overcome the reliability and manufacturing challenges, microprocessors using this technology will come close to achieving their maximum theoretical power-performance efficiency. In, researchers theorized that the lowest possible operating voltage for a CMOS circuit is 36mV, which some experiments have approached.
Although the experimental design exploits both instruction-level and data-level parallelism, the key to good performance scaling appears to be fine-grained thread-level parallelism.
This design requires programmers to explicitly create threads, but a dynamic thread manager supervises their execution, allowing a program to spawn more threads than the processor can execute at once.
To reduce the overhead of managing so many threads, the processor needs a hardware-accelerated synchronizer that eliminates deadlocks. Those are some early results of the Godson-T research project, a government-funded endeavor at the Institute of Computing Technology Chinese Academy of Sciences in Beijing.
Godson-T CPU-level block diagram. Godson-T chip-level block diagram. Godson-T simulation benchmark results. This processor will add hundreds of new instructions, including a set called Advanced Vector Extensions 2.
Also coming in Haswell are 96 fused multiply-add FMA instructions with a new three-operand format FMA3 , plus 16 new general-purpose instructions. All together, these "Haswell new instructions," as Intel calls them, herald the biggest xarchitecture expansion in years.
And even before Haswell, Intel will introduce seven new instructions with a processor code-named Ivy Bridge in Summary of Intel's recent and future x86 extensions. Ivy Bridge new instructions.
Haswell's new FMA instructions. Haswell's new general-purpose instructions. Intel Shows MIC Progress [Brief Item] Intel has demonstrated early hardware and software developed for its evolving manycore processors, which aim to expand the x86 architecture's dominance in supercomputers and high-performance computing.
Aubrey Isle die photo with overlay. Scheduled to begin sampling early next year, the AMP Advanced Multiprocessing series will debut with Freescale's first multithreaded CPU core, up to a dozen CPUs per chip, higher clock frequencies, faster offload engines, resurrected AltiVec extensions, and other goodies.
For control-plane processing, future T5-series chips with six CPUs will aim for clock speeds as high as 2. The company says its PowerShrink technology requires only minor modifications to existing bulk-CMOS processes and adds little cost, beyond licensing.
Although these claims naturally arouse skepticism, SuVolta has successfully produced SRAM test chips in 65nm and 28nm technology, and PowerShrink has been adopted by a major customer: Although intended primarily for notebook PCs and entry-level desktops, the company's new Nano QuadCore processor may also find its way into high-performance embedded systems and power-efficient servers.
Following a trend set by AMD and Intel, Via's first quad-core device combines two dual-core die in a single package. The pin multichip package NanoBGA2 is 21mm square, and it maintains pin compatibility with Nano X2 and several other Via processors: Intel refers to its FinFETs as tri-gate transistors and touts them as the first true three-dimensional devices built on planar integrated circuits.
Don't confuse these "3D" transistors with 3D transistor stacking, an entirely different technology that builds transistors in multiple layers. Instead, a FinFET rises above the flat silicon substrate, creating a 3D gate structure that has much more volume than a planar gate while squeezing into approximately the same horizontal space.
Gate-delay characteristics of FinFET and planar transistors. The company has also produced test chips in 28nm CMOS. Branded Itera, the new memory is licensed as intellectual property IP to chip designers.
It will be available for 55nm and 65nm processes in 3Q11 and for 28nm processes in 4Q Block sizes range from 32 bits to 1Mb, and write endurance ranges from to 1, cycles.
Packet-throughput performance doubles to 80Gbps, easily outrunning other multicore embedded processors. The bit XLP is designed primarily for data-plane processing in large routers, security appliances, storage subsystems, next-generation cellular networks, and other communications equipment.
At its fastest target clock frequency of 2. Key parameters for high-end network processors from Cavium, Freescale, and NetLogic. For the first time, metal-gate transistors are broadly available to chip designers, allowing them to create higher-performance microprocessors that can still occupy less silicon and consume less power.
This nanoscale application of metallurgy has been touted as the biggest advance in electronics since the invention of planar integrated circuits. As usual, Intel got there first.
In, Intel introduced the first microprocessors built in its new 45nm high - k metal-gate HKMG process. The rest of the semiconductor industry has been waiting four years for the same technology.
Chip shrinkage, 90nm to 28nm. Transistor evolution, nm to 28nm. One such idea is embedding a hardened CPU core in a programmable logic device. Now, Xilinx is trying again.
On March 1, the company announced the first products in its Zynq Extensible Processing Platform, foreshadowed last year in a joint announcement with ARM. TI Accelerates Video Processors [Brief Item] Texas Instruments TI has announced six DaVinci digital-media processors with faster video accelerators and higher integration, allowing a single chip to replace eight or more chips in some cases.
All the new processors unite at least one HD-video accelerator with an ARM Cortex-A8 CPU core and a TI Cx-series DSP, aiming for higher-end video applications such as surveillance systems, multiscreen videoconferencing, professional broadcasting, digital signage, and medical imaging.
Lower-power versions of the chips are also suitable for some consumer electronics. Both are designed for single - or dual-core implementations. Cortex-R7 is a radical departure from the norm: It's a dual-issue superscalar machine with an stage integer pipeline, instruction reordering, speculative execution, and optional symmetric multiprocessing.
ARM Cortex-R7 block diagram. Multicore coherence with Cortex-R5 and Cortex-R7. Although NetLogic disclosed basic information about the XLP during a large rollout of XLP processors last summer, the company didn't announce these variations at that time.
As smartphones, tablets, e-readers, and other mobile devices supersede PCs in the minds and pocketbooks of consumers, SoCs with licensable CPU architectures are emerging as the dominant species of microprocessor.
This year-end review article summarizes events in related to licensable embedded-processor cores and considers likely developments in Instead of building expensive six-transistor 6T or eight-transistor 8T SRAM cells in a logic process to accommodate the processor, Venray is moving the processor to commodity-DRAM processes, whose 1T memory cells are cheaper to manufacture and less leaky.
Venray's Aurora test chip. Block diagram of Venray's "Shirtbook" tablet. The new Atom EC series previously known as Stellarton is suitable for some low-volume embedded applications that need to wrap an x86 processor in application-specific logic.
For one, Fusion processors for desktop PCs aren't ready yet. Wait until next year. Second, the new processors aren't only for netbooks. If OEM customers want to use these low-power processors to build large-screen notebooks or even desktop PCs, AMD is happy to sell them the chips, no strings attached.
And third, despite the hype over smartphones and tablets, netbooks remain a profitable market segment in which AMD has no presence whatsoever. AMD Fusion block diagram.
AMD's first Fusion processors. Target applications include small-business routers, network-attached storage NAS controllers, digital-video surveillance systems, and industrial control-area networks.
Today, Cavium announced four new series in the bit Octeon II family, populating a product line that now spans an unprecedented range from 1 to 32 CPU cores per chip. The new brood fills the low-end to midrange Octeon II line, leaving no significant gaps.
Cavium's Octeon II family. Key parameters for Cavium's Octeon II family. Comparison of midrange networking processors. Comparison of low-end networking processors. Now, Altera is again using embedded CPUs as bait to lure the industry toward reconfigurable logic.
These choices span a broader range of implementation options than ever before. Developers will be able to choose a hard core the foundry builds the CPU in fixed logic on the same die as the programmable fabric, soft cores developers compile a synthesizable CPU for the fabric at design time, and the Intel multichip module which pairs an Atom processor with an Altera FPGA.
The licensable K is a fully synthesizable core, is portable to any foundry, and is available now. MIPS32 K pipeline diagram. Within a few years, the Chinese hope, an all-native machine will rule the Top list of the world's biggest iron.
Three new Godson chips are in development. Godson-3C will be the fastest new member of the family, as well as the most sophisticated Chinese microprocessor yet disclosed.
A third new chip, Godson-2H, is a smaller single-core design with integrated GPU, memory controller, and peripheral controllers. Intended for low-cost PCs, netbooks, and embedded systems, Godson-2H will also be manufactured in 65nm and is slated for production in 2H Milestones of Godson evolution.
Godson GSV block diagram. Extending DPAA to the lower-priced chips allows software developers to use the same code, tools, drivers, frameworks, and application programming interfaces APIs across the whole QorIQ family.
New processors in Freescale's QorIQ family. Atom has almost totally eclipsed Via Technologies' Centaur processors, which pioneered the concept of a smaller and simpler x Athlon Neo runs much hotter than Atom, and AMD's other x86 processors are optimized for high performance in servers, desktops, and mainstream notebooks.
Now, AMD is clawing back. Its newest CPU core, code-named Bobcat, should beat Atom in single-thread performance at similar subwatt power levels. AMD Bobcat block diagram.
Its new Opteron server processors are intended for cloud-computing data centers that buy servers by the truckload. Although they can't match Xeon's most power-efficient models, they offer a less expensive alternative while still going easy on the electricity.
In all, AMD has introduced nine new Opteron processors. AMD Opteron and Opteron block diagrams. Key parameters for AMD's new series server processors. Comparison of low-priced versions of Opteron and Xeon.
Nine new chips are scheduled to sample this fall, each with the four-way multithreading and four-issue superscalar features of the previously announced eight-core XLP The new chips have one, two, four, or eight CPUs.
At the high end of the family, the previously announced eight-core XLP will be joined by another eight-core chip, the XLP These two chips, which are designed for network infrastructure, scale from 10Gbps to Gbps.
Multithreading and superscalar execution in NetLogic's EC NetLogic XLP block diagram. NetLogic's interchip interface ICI. Free link to this article PDF: Tier Logic has operational samples of its first programmable-logic chips and has already taken orders from early customers.
The company had planned to begin production by the end of this quarter. New Networking Chips Will Exceed 2. Although Freescale will continue making bit processors for years to come, its new P5-series chips in the QorIQ family will introduce a bit Power Architecture core, which is capable of multigigahertz clock speeds.
Freescale Semiconductor's QorIQ family. Called Gusto, it's licensed as process-portable intellectual property IP. It's large enough to store boot code and system firmware, rather than just code patches, configuration code, and trim settings for analog components.
In addition, Kilopass claims Gusto reads memory two to four times faster, cuts active power consumption by an order of magnitude, and slashes current leakage in standby mode by a factor of Two-transistor antifuse bit cell.
Antifuse bit-cell circuit diagrams. Electron micrograph of a Kilopass 2T antifuse bit cell at 40nm. XPM versus Gusto area comparison. Integration comparison of two hypothetical smartphones.
Comparison of nonvolatile-memory NVM technologies. Intel Adapts Larrabee for HPC [Brief Item] Intel's troubled manycore-processor project is steering away from discrete 3D graphics in favor of high-performance computing HPC, mainly for scientific and engineering applications.
It's a wise maneuver that will salvage Intel's investment in the Larrabee project, and the new direction is better suited to Intel's experience and expertise. But it won't avoid a collision with Nvidia, which is surging into the same market.
The xbased family of GPUs code-named Larrabee will spawn a new family of manycore processors code-named Knights. Both Larrabee and Knights can integrate dozens of x86 processor cores on a single chip.
The platform is intended for high-end smartphones, tablet computers, and the handheld computing devices that Intel formerly called mobile Internet devices, or MIDs. It will compete with processors designed for trendy products like the Apple iPhone, Nexus One, and Nokia N, but probably not with more-integrated processors designed for mainstream smartphones, like the Blackberry Bold and Blackberry Curve.
Menlow versus Moorestown integration. Die-photo comparison of Lincroft versus Silverthorne. Thermal images of Lincroft in two different power states. Forecast of smartphone processor shipments from to Power states for systems built with Intel's Moorestown chip set.
Estimated battery life of a Moorestown smartphone. Comparison of Intel's Moorestown with leading smartphone processors from Texas Instruments and Qualcomm. Moorestown Goes Embedded Sidebar: Decoding Intel's Code Names Editorial: Smartphone Spectrum Disorder Broadcast television in America, once described as a vast wasteland, now looks more like prime real estate.
Or rather, the radio-frequency spectrum that broadcast TV occupies is the suddenly valuable property. So valuable that some people in the telecommunications industry want to seize all that RF spectrum for wireless telephony and banish terrestrial TV broadcasting to the dustbin of history.
However, the real issue isn't the alleged obsolescence of broadcast TV. The wireless telcos and handset vendors are painting a marvelous vision of the future in which everyone carries a wireless device that delivers a dazzling array of features and services.
Unfortunately, there isn't enough spectrum available to make the vision come true. To differentiate its products and justify their higher prices, Apple must do more than wrap trend-setting industrial design and slick system software around other suppliers' standard parts.
By developing custom SoCs and embedded-processor cores, Apple is assuming more risk, but the potential payoffs are great: Now, Apple is absorbing Intrinsity, a small Austin-based company that sells embedded-processor cores, circuit-design tools, design services, and innovative intellectual property.
It's based on a 1. ARM Cortex-M4 block diagram. With these devices, the third spatial dimension exists for only a split-second slice of time. Tabula's devices can completely reconfigure their fabrics up to 1.
That's about one million times faster than conventional FPGAs. Rapid reconfiguration makes the physical fabric seem much larger than it really is. Tabula's first-generation chips can reuse the same physical gates for as many as eight different functions.
By rapidly reconfiguring the fabric, each physical gate can perform up to eight different functions. Tabula uses time to emulate the third spatial dimension, making one fabric seem like eight fabrics stacked together.
Each configuration is called a "fold" because it folds time into space. Tabula uses transparent latches as "time vias" to pass signals forward in time from one fold fabric configuration to another.
In a Tabula chip, time isn't linear. It's an endless loop, because the last fold wraps around to the first fold. The virtual stack is really a torus. Tabula's first-generation devices run at 1.
As chip-fabrication technology improves, Tabula's 3PLDs may derive greater benefits from Moore's law. Faster clock speeds allow Tabula to add more folds to its virtual 3D fabric. This has implications for interconnects, as well as for gate density.
Although Tabula's chips use single-ported SRAM instead of dual-ported SRAM for user memory, different function blocks can independently access the same memory during each fold.
Physical layout of logic tiles in a Tabula 3PLD. Ellen Clements It is with great sadness that we report the passing of our longtime colleague, Ellen Clements. Few readers of Microprocessor Report are familiar with Ellen, because her name didn't appear in the newsletter.
Yet, for 17 years, Ellen was one of the people who worked behind the scenes to ensure its quality. I was fraud until today the box was open and my surprise is that in the interior theres no phone buy only a clay.
Si this a fraud o what need an answer. Read this if you are thinking of switching from Android!!! So I made the switch from using Android to the iPhone back in October, and I've been using the iPhone 6 for the past few months now and can give a detailed review on what it's like to switch over.
Before this switch, I've used the Samsung Galaxy S2 first smartphone ever! Here are my thoughts: Things that the iPhone does really well both hardware and software-wise: The behind the scene software for digitally capturing an image is definitely the strongest sell for the iPhone.
Other than the S5 and Note 4, no smartphone really comes close to having the same kind of image quality no matter the megapixels compared to the iPhone. This was one of the reasons for me to switch over since I've started to dabble with photography and wanted a really good camera in my smartphone.
Side note, if you read a lot of tech blogs, there is a notion that in the near future our smartphones won't accurately describe our devices anymore since making a phone call is probably one of the least commonly used features on a smartphone when you look at any average user.
Cameras, social media, emails all take a higher usage rate than making a call There have been maybe 2 or 3 times when my phone crashed and would have to be restarted, mostly due to playing some game that was not written very well for the iOS devices.
On Android devices, I've experienced a lot more crashes, and that may be due to the fact that so many apps haven't figured out the best way to optimize the app for each individual phone due to the fragmentation problems or something else.
Either way, I feel like the iOS environment and hardware is more reliable in my everyday use. Once you've used it, you won't go back. The S5 is not that close yet in terms of usability with their sensor.
The one in the iPhone 6 works really well. I definitely have found myself using my phone more because of how easy it is to unlock and install apps. This is an interesting point.
In general, you get way more control over how to use and how to integrate your apps on Android than iOS. But in iOS, it's really interesting that you can control the kind of notification that gets sent to your phone, background refresh, location requirement, and access to certain things like photos and camera.
In Android, you can do all of this as well, but sometimes for a lot of apps you have to have root access. Double tap to bring down the row of apps. I can't believe no one has thought of this before.
A lot of Android phones have gigantic screens, but no one has really figured out how to best get the users to interact with that. You can tap the home button twice on the iPhone to bring down the top few rows of the apps so that you can access them in one hand use.
Here are the things that I miss on Android: Full integration of almost any apps and control of default apps. I can set default apps on Android whereas Apple does not allow that. I can open up photos and upload them to Dropbox or any other app that I choose to, whereas Apple doesn't allow uploading to Dropbox via the Photos app you have to open up Dropbox, then select upload and then go to Photos from there.
In the mail app for Android, you can attach almost any file on the phone. You can't do that on Apple. You can't even attach a single file. You have to share a file as an email.
So, forget about replying an email with an attachment. This is pretty annoying. Productivity is better on Android. If you are a big dropbox user, you probably know and love Dropsync on Android seriously, best 5 bucks spent on any app.
You can have an app that syncs and download any material from Dropbox onto your Android and then sync it back up when changes are detected. Apple does NOT allow that mainly because they don't allow background apps from accessing the hard drive, or something along those lines.
So you have to download the file you are interested in manually from the Dropbox app. It just slows you down a lot, especially if you get to a part of a building where there is weak signal for wifi or cellular data.
Notifications are way better. Why can't Apple make one button that clears all of your notifications? You have to individually close each app's own notification. I pretty much leave my notification screen untouched.
Some other things that many already know: Material design looks awesome! Way better widgets and the fact that you can have widgets!! Oh, and you can swipe right on the home screen on Android and that brings another screen from the left side More customization and etc.
Overall, I think the iPhone is a fine device to use and you probably won't regret investing in one. The customer service from Apple is top notch, even if their parts cost an arm and leg.
I think that, and I hate to say this because it's going to sound like every blog writer out there, the choice really does come down to personal preference and what you use the phone for.
So, I've broken down my recommendation based on user case scenarios: If you are user type The integration with all the apps and the feature with dropbox is just so important to anyone who works on their phones and other mobile devices.
I would either get a pure Google device N5 or N6, I like smaller phones Samsung and HTC are also good choices but updates may be slow. One Plus One is actually pretty cool. They are not the best when it comes to customer service since they're a small company filling huge demand, but from my experience, the device is solid and definitely a work horse.
Medical and Science community: Unfortunately, most of the med and science people rely on Apple products, and a lot of new apps still come to iOS first or are better updated and designed on iOS.
Recreational, use a phone as a communication device and for fun: The camera and social apps are fun to use on the iPhone. This is a split. If you've used Apple products before, then iOS will be easy to learn.
Android phones have gotten a LOT easier to use thanks to a big push from Google dealing with not only the UI from a software perspective but also from a design perspective.
It is more intuitive than it used to be. Samsung's camera is great, but the company is known to really bog down their stellar devices with bloatware that ruins or significantly slows down your phone after 1 year of use.
So was this the right switch for me? As I'm learning more about the iPhone and iOS, I've realized that when the two year is over or whenever this phone dies on me, I'll most likely switch back to Android.
While I think I've been thoroughly spoiled by the fingerprint sensor, the productivity that I enjoyed on Android just doesn't replicate itself here on the iPhone.
Maybe it's not meant to be a super productive machine, but I guess my main point is that I'd like to have that option available when I need it. And I do understand that a lot of people enjoy doing this and can get their phones to work fantastically well.
I used to do a lot of customization and go through ROMs once every three days on my Android devices, but I've come to realize that I'd rather spend that time using the device than customizing it.
So, nowadays, I just want my devices to work right out of the box. The little details like a great camera, fingerprint sensor, and the ability to have my dropbox synced on the go and a good notification system should all be there when I turn on my phone.
Summary and TL; DR: So there you have it. An Android user's thoughts on using the iPhone 6. Do I have regrets switching over? But for now, the iPhone 6 suits my needs, even if there are occasional frustration points.
If you are an Android user, please consider all these points and google similar stories before switching. Also, I'm one of those workaholics and forever in search of super productivity, hence my review that I'd like to go back to Android.
However, I know plenty of people who swear by their iPhones for productivity. If you are always connected and depend on a suite of iOS specific apps including apps that are better designed or work better on iOS, then chances are you love the iPhone.
There are plenty of things to like and love about either OS. It really does come down to personal preference. It allows you to sign into your Exchange, Outlook accounts as well as your Gmail, Yahoo, and iCloud emails.
Once integrated, you can attach any file located in those drives, which is great! You can also attach files that are attached in emails that are already in your inbox! And, you can now reply an email with the option of attaching a file.
Finally, you can decide if you want to open up links from emails in Safari or another browser installed on your phone so, you are no longer bound by default Apple apps. This is a huge step forward, and it's from Microsoft a pleasant surprise.
There are still kinks when switching over if you are used to productive flexibility on Android phones, but right now the 3rd party apps are getting better and better at work-arounds.
The iPhone 6 has served me well over the past two years, but I've made the upgrade to the iPhone 7 a few months ago. If you are interested in reading about my thoughts on the iPhone 7, you can read my review here on Amazon https: Bought an iPhone 6s gb!
I came in 2 days. It had everything else except the phone! Who would do this? See all 3, reviews. See all customer images. Most recent customer reviews. Published 13 hours ago. Published 18 hours ago.
Published 21 hours ago. Published 1 day ago. Published 3 days ago.
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Equally important to Big Blue, Power8's performance is energizing the OpenPower Foundation, an IBM-led alliance that rallies other companies to create a larger hardware and software ecosystem around the processor.
IBM is offering Power8 chips to system builders in the merchant semiconductor market and is even licensing the architecture to other processor vendors. IBM Power8 processors for the merchant market.
Although the dollar amount was undisclosed, it will strengthen the startup's position versus established rivals like Sonics and Arteris. NetSpeed also faces growing competition from ARM, whose licensable cache-coherent interconnects are becoming more sophisticated and are encroaching on some territory the NoC vendors have staked out.
The growing complexity of SoC designs is creating more opportunities for licensable NoCs. NetSpeed's NocStudio configuration tool. Orion versus Amba AXI. Two Gemini NoC implementations. All are compatible with the bit ARMv8 architecture.
Those single - and dual-core chips are highly optimized for packet processing and communications. By contrast, Helix chips have two, four, or eight bit CPUs, and we believe they have much of the same packet acceleration as the PacketPro Mamba and Diamondback processors.
Block diagram of AppliedMicro's Helix 2 embedded processor. Feature comparison of AppliedMicro's Helix embedded processors. Despite their maximum target clock frequency of 1.
Applications include integrated-services branch routers, security appliances, industrial controllers, and edge devices that implement software-defined networking SDN and network-function virtualization NFV.
It is the most powerful implementation of the ARCv2 instruction-set architecture. Targets include Wi-Fi routers, Internet gateways, digital TVs, smart appliances, and advanced driver-assistance systems.
Consequently, it can run a virtual-memory operating system, such as full versions of Linux. The bit synthesizable CPU also supports dual - and quad-core clusters with cache-coherent symmetric multiprocessing SMP.
Yet it retains the user configurability, low power consumption, and small size of its ARC predecessors. Simulations indicate the HS38 will deliver a maximum worst-case clock frequency of 1.
The typical clock frequency in that process is 2. KeyStone Targets Industrial Apps [Brief Item] Texas Instruments is sampling four KeyStone II processors it originally announced two years ago and is extending their temperature range for industrial and military-aerospace applications.
Although they are intended mainly for networked industrial applications, their switched Ethernet ports and optional DSP also suit them to enterprise gateways.
General sampling began in September, and production is scheduled to start by the end of this year. In fact, this is the first processor we've seen that uses Micron's stacked-memory cubes.
And the core counts are doubling with each generation. Sparc64 XIfx die photo with overlay. Block diagram of Sparc64 XIfx core groups. The next-generation Sparc M7 weighs in with more than 10 billion transistors on a die we estimate at about mm 2.
Each of its 32 CPU cores can simultaneously execute eight threads, and the chip has more than 70MB of cache. What to do with this monster? Run Oracle's database software, of course.
Since Oracle acquired Sun Microsystems in and took over SPARC development, it has executed a surprisingly aggressive roadmap that has new processors coming out every year. Because Oracle is virtually the only customer for these processors, the architects can tune them for the company's famous enterprise software.
Oracle Sparc M7 die photo. Sparc M7 performance versus Sparc M6. The new chips began sampling in 1Q14 and are scheduled for production in 4Q Block diagram of Broadcom's BCM Key parameters for Broadcom's BCMx5 base-station processors.
Like their forebears, the new processors target a broad range of embedded applications, but they focus on real-time industrial communications, test-and-measurement instruments, barcode scanners, portable data terminals, medical devices, and GPS navigation.
TI's new Sitara AMx series: Those are the code-names for six new Embedded G-Series SoCs that will go talon to talon with Intel's Atom and other high-performance embedded processors.
Although AMD is optimistically pitching the new dual - and quad-core chips for data-center switches and network-security appliances, their main markets are PC-like embedded systems: Such systems commonly employ x86 embedded processors derived from PC processors and usually run Windows or Linux.
The new chips are in production now, and their clock speeds of 1. Its escort is the Armada, a single-core model based on the same die. Both processors target small-business, enterprise, and carrier-class communications equipment, such as Marvell Armada block diagram.
Example Wi-Fi access point using the Armada and other Marvell chips. Comparison of Marvell's Armada, , , and Mindspeed, which originated as a Conexant spinoff in, has now been chopped into three pieces.
Macom is retaining Mindspeed's extensive analog portfolio and Comcerto voice-over-IP VoIP processors but is selling the Comcerto gateway processors to Freescale for an undisclosed sum.
The T is a quad-core eight-thread processor optimized for midrange communications infrastructure, and the others are single - and dual-core processors optimized for low-end communications and general embedded applications.
These eagerly awaited 28nm chips fill several gaps in the QorIQ T-series, finally superseding some popular but aging P-series processors manufactured in 45nm technology. QorIQ T block diagram.
The new XLP series comprises three basic models with four, six, or eight CPU cores and two package options, for a total of six distinct products. The faster network interfaces launch these midrange products into the same stratosphere as previous-generation high-end processors.
Previously, only high-end communications processors supported 40GbE interfaces. Doubling the number of CPU cores and threads will help these muscular devices handle the faster packet flows.
Block diagram of Broadcom XLP An XLP wireless base station. Small-cell LTE base station. Freescale's QorIQ Qonverge family. Key parameters for Qonverge B, B, and B processors.
Freescale's Qonverge B versus two competitors: Microchip designed the PIC32MZ family for high-end controller applications, such as vehicle dashboard systems, building environmental controls, and consumer-appliance control modules.
Our analyst team is deeply familiar with all the leading processor products, having written about them for Microprocessor Report over the course of the past year.
Intel C family Best Processor Technology: For now, though, embedded processors are athletes in the prime of life, achieving record-breaking performance. Cavium's core Octeon III, another 28nm giant, has yet to sample.
Two additional trends apparent in were further movement toward the ARM architecture and bit processing. Tilera's Tile-Gx posted the highest single-socket CoreMark score.
Although the processor giant is saying little about the deal, it has acquired Mindspeed's inventories and intends to fulfill the product roadmap, including the new Transcede T and T base-station processors announced last year.
Before Intel's December 16 offer, Mindspeed's wireless business looked precarious. Although Mindspeed's analog technology was a desirable acquisition target, Macom had no interest in the base-station processors.
Had Mindspeed not found a buyer for those processors, Macom would have discontinued them. SEC filings suggest that Mindspeed was already negotiating their sale to Intel before Macom tendered its bid for the rest of the company.
Future members of the IPQ family will target other network-edge devices, such as small-business access points and small-cell base stations. Although these markets are already crowded with major competitors, Qualcomm hopes to succeed by applying its experience in related fields, such as smartphones, cellular base stations, Wi-Fi access points, and Ethernet switching.
The IPQ is the primary product; the other chip is a slightly slower and lower-cost subset. Scheduled for production in 1Q14, this first xCore-XA device will be followed by additional models having slightly different features.
Although other xCore chips can handle both tasks, ARM compatibility lets developers use their existing code for the higher-level software while running optimized control code on the proprietary core.
Simulations indicate it will reach clock frequencies of up to 1. But clock speed isn't the only selling point: ARC HS cores also improve power efficiency, silicon area, code density, integer throughput, floating-point performance, and real-time trace features.
The other new CPU, the ARC HS36, is intended primarily for higher-end mobile consumer products, such as digital cameras and tablets, as well as for digital TVs, set-top boxes, automobile infotainment systems, and the "Internet of Things" noncomputer devices.
ARC HS block diagram. ARC HS instruction pipeline. The P is the first member of the Series5 Warrior family and is designed for consumer electronics, smartphones, tablets, and other high-performance embedded systems.
It's a licensable and synthesizable bit CPU core with a stage instruction pipeline, four-issue superscalar execution, instruction reordering, improved branch prediction, extended memory addressing, and hardware virtualization.
Its bit dual-issue SIMD units can handle single - and double-precision floating-point operations as well as integer data types. By pairing some operations, the P can effectively issue up to eight instructions per clock cycle.
MIPS P block diagram. MIPS P load pipeline. MIPS P six-core coherent cluster. Comparison of high-performance bit CPU cores. IDC estimates that compact-digicam sales will plunge to 80 million units this year from million in In comparison, The Linley Group forecasts million smartphones will sell this year.
Now, a major sensor supplier is promising higher quality and greater light sensitivity with smaller pixels. Comparison using Macbeth color chart. The classic Bayer color-filter array versus four alternatives.
Intel Tests Code Compression [Brief Item] Intel Labs has demonstrated a compile-time code-compression technology in which a processor unpacks the compressed program at run time.
The goal is to cut silicon costs by reducing the amount of on-chip memory. Although Intel calls the technology "direct compressed execution," the compressed program is actually decompressed on the fly before execution.
It differs from other code-compression techniques such as ARM's Thumb that replace bit instructions with bit opcodes. Instead of using a modified instruction set, programmers write, compile, and link their code as usual, then employ a special utility to compress the binary file.
Slated for production this fall, these multichip MCUs are intended mainly for high-end audio gear, automobile infotainment systems, factory robots, and other industrial applications. Moreover, the CPUs support hardware multithreading with up to eight threads per core.
These threads which XMOS calls "logical cores" share equal time by executing in a deterministic round-robin fashion, switching contexts on every clock cycle. Three families of XMOS bit microcontrollers.
Sporting 20 CPU cores running at 2. Moreover, a special interchip interface can unite a maximum of eight processors in a cache-coherent cluster whose total throughput is 1.
With its cryptographic engines, regular-expression reg-ex acceleration, RAID acceleration, packet accelerators, and compression engines, it can manage routing, switching, security processing, load balancing, and cloud storage.
New virtualization features open doors into data-center processing. Broadcom XLP block diagram. MIPS64 Release 5 virtualization. Broadcom's Interchip Coherency Interface. Comparison of high-end communications processors: They also retain the integrated Gigabit Ethernet switches that set this family apart from other embedded processors.
Their primary markets are enterprise access points and small-business Wi-Fi routers. Both new StrataGX processors have dual 1. The new high-end chip in the family is the BCM, intended mainly for enterprise Wi-Fi access points.
When paired with Broadcom's Ethernet switch chips, it can also handle control-plane processing and cryptography acceleration. Key parameters for Broadcom's StrataGX processors.
Designed for low-cost storage control, media servers, and light-duty networking, the surpasses other Armada series chips and measures up to processors in the higher-end Armada XP family.
With the S family code-named Centerton, the company has extended Atom into servers as well. The S and S processors run at 1. They began production in 1Q Although the informal "law" has brought the industry vast fame and riches, complying with its rigid demands and relentless schedule is becoming enormously expensive.
It is also forcing researchers to experiment with increasingly extreme technologies, in turn forcing chip designers to face a more confusing array of choices. The growing costs and complexity of chip manufacturing were evident at two recent foundry events in Silicon Valley.
The roadmaps unveiled at these events are vital information, because almost all chip companies have committed to a fabless or "fab-lite" business model that outsources manufacturing.
Relative costs of new process technologies. Comparison of four GlobalFoundries process technologies. To support these claims, the company released 17 world-record benchmark results.
It also achieves top scores on several database, middleware, and system-level benchmarks appropriate for Oracle's enterprise-server business. Sparc T5 die photo with overlay. Foremost were new base-station processors from Broadcom and Mindspeed.
Mindspeed announced two second-generation dual-mode designs, the Transcede T and T New base-station processors from Broadcom and Mindspeed. This monolithic design is a unique achievement of manycore integration in 40nm CMOS technology.
Each CPU has a maximum clock frequency of 1. The mesh arranges the CPUs in an eight-by-nine tiled matrix that provides more than terabits per second of aggregate bandwidth.
The company has announced three new chips that will challenge the dominant market leader, Cavium's Nitrox family. Freescale's new C29x chips join additional newcomers: Intel's DHfamily "Cave Creek" chips, which were introduced last quarter.
Why is Freescale entering this market now? For one thing, the company expects demand for public-key cryptography performance to rise as the industry switches from the widely used 1,bit keys to the safer 2,bit keys recommended by the U.
Also, the dearth of competition has convinced Freescale that there's room for a lower-priced product. Example system design based on Freescale's C29x. High-performance crypto coprocessors from Freescale, Cavium, and Intel.
For its achievements in replacing conventional clock-signal trees with a resonant clock mesh and easing the design of high-performance chips, Cyclos nets The Linley Group's Analysts' Choice Award for the best new microprocessor-related technology of High-speed processors impose many design challenges, not the least being the rising power consumption of complex clock trees.
Essential for uniform timing, these circuits have numerous branches that carry clock signals to every nook and cranny of a chip. But as processors get faster and more complex, clock trees struggle to keep up and can account for one-third of the chip's power consumption.
The leading alternative, especially for processors exceeding 2. Cyclos reduces power consumption in clock meshes by connecting them with integrated inductors to form resonant LC oscillators. Lawyers dream of rewriting landmark court rulings.
Engineers dream of redesigning microprocessor architectures. But such opportunities are so rare that few practitioners ever get a chance to make such fundamental changes.
Starting in, some lucky engineers at ARM got that chance. Nevertheless, they got a once-in-a-lifetime opportunity to overhaul an architecture that remains quite serviceable but has some crufty features that impair performance.
Since we first covered ARMv8 last year, the company has released much more documentation, allowing a more thorough analysis. Although ARM's tardiness in moving to 64 bits has undoubtedly cost the company some opportunities, ARMv8 is an extensive revision, and the delay has allowed ARM's architects to learn from other companies' experience and mistakes.
ARMv8's privileged-execution model in AArch ARMv8's bit memory map. ARMv8's optional cryptography instructions. These tiny chips squash the list price of bit MCUs to as little as 39 cents each in 10,unit volumes.
It seems impossible that a bit MCU could cost so little and function with only eight pins. But then, no other processors can match the credentials of Texas Instruments' new KeyStone chips: Just about the only thing TI left out is cellular-baseband acceleration, distinguishing these chips from the company's KeyStone II base-station processors.
Broadcom is also sampling six newly announced processors: Note that some of these chips have the same names as previous XLP chips fabricated in 40nm technology.
All the new XLP II processors are single - or dual-core chips with one to eight threads and a target clock frequency of 2. But at 12MHz, it uses only 2. The key to prolonging battery life is to sleep as much as possible, then quickly wake up and do a brief burst of work before slumbering again.
In deep sleep, only the real-time clock RTC remains awake. It can supervise simple tasks without disturbing the CPU, because the peripherals have some autonomy. Whereas Fujitsu's tenth-generation Sparc64 X design emphasizes per-thread throughput, Oracle's Sparc T5 excels at multichip scaling.
This article focuses on Fujitsu's processor, for which more information is available. Oracle was more reticent but did reveal some new features. These companies are the only remaining developers of high-performance SPARC processors and are their own biggest customers.
Fujitsu Sparc64 X die photo. Sparc64 X instruction pipeline. Sparc64 X multichip interconnects. Oracle's Sparc T5 multichip configuration. DesignArt's 4G base-station processors surpass Qualcomm's existing 3G femtocell products by offering much higher data rates and user capacities.
In addition, Qualcomm gains DesignArt's important wireless-backhaul technology and a respected engineering team. DesignArt is an Israeli fabless semiconductor company founded in Well, not quite, but it seems that way.
The latest chips to come within ARM's reach are Freescale's market-leading QorIQ communications processors, which are also the best-selling flag bearers of the Power Architecture. Freescale's Layerscape chip-level architecture.
Freescale Targets Smaller Cells [Brief Item] Integrated processors for wireless base stations continue to proliferate. These chips are pin compatible and the first Freescale products to sample in 28nm HPM technology.
Samples are due in 3Q12, with production scheduled for 2H First, China wants to standardize on a single instruction-set architecture for all future government-sponsored projects.
These events lead me to suggest that the Chinese government or one of its semiprivate entities should acquire MIPS. But when judged purely as a business and technology proposition, the deal makes more sense than many other scenarios.
The latest additions are the quad-core P, which has twice as many CPU cores as previous P5-series chips, and the dual-core P, which improves on the existing P Both new processors also add more Ethernet controllers and raise the maximum clock speed of their Power e CPU cores to 2.
Having twice as many CPUs as the existing P, the P bolsters Freescale's offerings for control processing and will improve the company's competitive stance against Intel's new Ivy Bridge embedded processors.
Freescale QorIQ P block diagram. Parallelism for the Masses Intel's "River Trail" Adds Easy Parallel Processing to JavaScript Unlocking the parallelism of multicore processors has vexed the industry since the first such chips burst onto the scene in With a project code-named River Trail, Intel Labs is taking a refreshingly different approach.
Intel's proposed JavaScript extension is so abstract that programmers need know nothing about the system's hardware. At run time, the web browser's modified JavaScript engine automatically discovers and adapts to any parallel-processing resources available.
It can use the CPU's vector-arithmetic instructions, multiple CPU cores per chip, multiple threads per core, and multiple processors per system. The latest experimental version can even assign tasks to some integrated GPUs.
River Trail demo screen. Parallelism with River Trail. One purpose for dual-band operation is to support the future Another dual-band scenario is a single client transmitting 2.
The multicore chips with dual ARM cores can independently run high-level application code and low-level control code. One multicore Vybrid chip can replace at least two separate chips while keeping software development on a common bit ARM platform.
But the new chip aims significantly higher, and system designers can link multiple chips together to build even larger base stations. TI's KeyStone integrated base-station processors.
Chips eliminated from a conventional base station design. Key parameters of integrated base-station processors: By skipping the tedious steps of translating marketing concepts into gate-level logic, the new PowerSynth tool makes design engineers obsolete and allows anyone to be a CPU architect.
PowerSynth uses patented artificial-intelligence algorithms to generate production-ready logic from common PowerPoint drawing objects. Typical SoC blockhead diagram. The B will bring CPU-DSP integration to large cellular base stations and is among the company's first chips manufactured in 28nm technology.
Two contrasting designs for LTE macrocell base stations. Key features of high-performance DSP cores: Freescale's QorIQ Qonverge family: An instruction set composed almost entirely of bit instructions.
Are we in the disco days of the s? Nope, it's, and ARM is introducing a new bit CPU core that plumbs the depths of simplicity and low power consumption. Even by RISC standards, a bit design can't get much simpler than this.
Although it uses less power than a Cortex-M0, it wears a plus sign instead of a minus because it adds features. The T is a highly integrated design with 12 CPU cores arranged in three quad-core clusters.
By contrast, the biggest existing QorIQ design is the eight-core P Moreover, the T debuts Freescale's new bit Power e dual-threaded CPU core, whereas the P uses the bit Power emc single-threaded core.
The new CPU, apart from other features, ensures that the T will be a much more powerful processor. QorIQ T multithreading performance. Power e CPU cluster. Wireless Wants to Wallop Wires Emerging The draft specification is close enough to final that companies like Broadcom, Quantenna, and Redpine Signals are already introducing the first The big news about We've heard such claims before, but Comparison of antenna technologies: Data rates for Broadcom's BCM43xx transceiver chips for Nevertheless, the design win helps establish Armada as an up-and-coming product line for smart TVs, Blu-ray players, and advanced set-top boxes.
Our pick for Although engineers have been working for years on the concept of three-dimensional ICs, new developments in virtually guarantee that stacked-memory devices are finally on their way to commercial production in the near future.
Other technologies we considered for this award are noteworthy, too. We nominated four candidates from Intel: The first commercial devices will stack four DRAM die connected using through-silicon vias.
This asymmetric or heterogeneous multicore design combines the high performance of application processors with the real-time response of microcontrollers. The new chips can be considered application-class SoCs with real-time credentials or bit MCUs with application aspirations.
By contrast, ARM's Big. Little strategy integrates a Cortex-A15 "big" core with a Cortex-A7 "little" core and is designed to save power in mobile application processors. Freescale AeMPU simplified block diagram.
In fact, they probably are derived from last year's smartphone processors. And if Xilinx prepares to send a man to Mars, Altera will start building rockets. The two leading FPGA vendors are that competitive.
So it's no surprise that Altera has announced its answer to Xilinx's Zynq chips, which are customizable SoCs that integrate ARM Cortex-A9 cores and hard peripherals with programmable logic.
But Altera isn't a copycat, because both companies are hearing the same pleas from customers and are building on experience with similar products introduced more than a decade ago. To keep the heat on rivals like Cavium, Freescale, and Intel, NetLogic must keep its transition to a new product line and 28nm technology on schedule.
NetLogic's Interchip Coherency Interface supports four - and eight-chip memory-coherent clusters. The STM32 F4 series includes four basic designs with various integrated peripherals.
Prototype chips are promising enough that commercial products may be only a few years away. If Intel can overcome the reliability and manufacturing challenges, microprocessors using this technology will come close to achieving their maximum theoretical power-performance efficiency.
In, researchers theorized that the lowest possible operating voltage for a CMOS circuit is 36mV, which some experiments have approached. Although the experimental design exploits both instruction-level and data-level parallelism, the key to good performance scaling appears to be fine-grained thread-level parallelism.
This design requires programmers to explicitly create threads, but a dynamic thread manager supervises their execution, allowing a program to spawn more threads than the processor can execute at once.
To reduce the overhead of managing so many threads, the processor needs a hardware-accelerated synchronizer that eliminates deadlocks. Those are some early results of the Godson-T research project, a government-funded endeavor at the Institute of Computing Technology Chinese Academy of Sciences in Beijing.
Godson-T CPU-level block diagram. Godson-T chip-level block diagram. Godson-T simulation benchmark results. This processor will add hundreds of new instructions, including a set called Advanced Vector Extensions 2.
Also coming in Haswell are 96 fused multiply-add FMA instructions with a new three-operand format FMA3 , plus 16 new general-purpose instructions. All together, these "Haswell new instructions," as Intel calls them, herald the biggest xarchitecture expansion in years.
And even before Haswell, Intel will introduce seven new instructions with a processor code-named Ivy Bridge in Summary of Intel's recent and future x86 extensions.
Ivy Bridge new instructions. Haswell's new FMA instructions. Haswell's new general-purpose instructions. Intel Shows MIC Progress [Brief Item] Intel has demonstrated early hardware and software developed for its evolving manycore processors, which aim to expand the x86 architecture's dominance in supercomputers and high-performance computing.
Aubrey Isle die photo with overlay. Scheduled to begin sampling early next year, the AMP Advanced Multiprocessing series will debut with Freescale's first multithreaded CPU core, up to a dozen CPUs per chip, higher clock frequencies, faster offload engines, resurrected AltiVec extensions, and other goodies.
For control-plane processing, future T5-series chips with six CPUs will aim for clock speeds as high as 2. The company says its PowerShrink technology requires only minor modifications to existing bulk-CMOS processes and adds little cost, beyond licensing.
Although these claims naturally arouse skepticism, SuVolta has successfully produced SRAM test chips in 65nm and 28nm technology, and PowerShrink has been adopted by a major customer: Although intended primarily for notebook PCs and entry-level desktops, the company's new Nano QuadCore processor may also find its way into high-performance embedded systems and power-efficient servers.
Following a trend set by AMD and Intel, Via's first quad-core device combines two dual-core die in a single package. The pin multichip package NanoBGA2 is 21mm square, and it maintains pin compatibility with Nano X2 and several other Via processors: Intel refers to its FinFETs as tri-gate transistors and touts them as the first true three-dimensional devices built on planar integrated circuits.
Don't confuse these "3D" transistors with 3D transistor stacking, an entirely different technology that builds transistors in multiple layers. Instead, a FinFET rises above the flat silicon substrate, creating a 3D gate structure that has much more volume than a planar gate while squeezing into approximately the same horizontal space.
Gate-delay characteristics of FinFET and planar transistors. The company has also produced test chips in 28nm CMOS. Branded Itera, the new memory is licensed as intellectual property IP to chip designers.
It will be available for 55nm and 65nm processes in 3Q11 and for 28nm processes in 4Q Block sizes range from 32 bits to 1Mb, and write endurance ranges from to 1, cycles.
Packet-throughput performance doubles to 80Gbps, easily outrunning other multicore embedded processors. The bit XLP is designed primarily for data-plane processing in large routers, security appliances, storage subsystems, next-generation cellular networks, and other communications equipment.
At its fastest target clock frequency of 2. Key parameters for high-end network processors from Cavium, Freescale, and NetLogic. For the first time, metal-gate transistors are broadly available to chip designers, allowing them to create higher-performance microprocessors that can still occupy less silicon and consume less power.
This nanoscale application of metallurgy has been touted as the biggest advance in electronics since the invention of planar integrated circuits. As usual, Intel got there first. In, Intel introduced the first microprocessors built in its new 45nm high - k metal-gate HKMG process.
The rest of the semiconductor industry has been waiting four years for the same technology. Chip shrinkage, 90nm to 28nm. Transistor evolution, nm to 28nm. One such idea is embedding a hardened CPU core in a programmable logic device.
Now, Xilinx is trying again. On March 1, the company announced the first products in its Zynq Extensible Processing Platform, foreshadowed last year in a joint announcement with ARM.
TI Accelerates Video Processors [Brief Item] Texas Instruments TI has announced six DaVinci digital-media processors with faster video accelerators and higher integration, allowing a single chip to replace eight or more chips in some cases.
All the new processors unite at least one HD-video accelerator with an ARM Cortex-A8 CPU core and a TI Cx-series DSP, aiming for higher-end video applications such as surveillance systems, multiscreen videoconferencing, professional broadcasting, digital signage, and medical imaging.
Lower-power versions of the chips are also suitable for some consumer electronics. Both are designed for single - or dual-core implementations. Cortex-R7 is a radical departure from the norm: It's a dual-issue superscalar machine with an stage integer pipeline, instruction reordering, speculative execution, and optional symmetric multiprocessing.
ARM Cortex-R7 block diagram. Multicore coherence with Cortex-R5 and Cortex-R7. Although NetLogic disclosed basic information about the XLP during a large rollout of XLP processors last summer, the company didn't announce these variations at that time.
As smartphones, tablets, e-readers, and other mobile devices supersede PCs in the minds and pocketbooks of consumers, SoCs with licensable CPU architectures are emerging as the dominant species of microprocessor.
This year-end review article summarizes events in related to licensable embedded-processor cores and considers likely developments in Instead of building expensive six-transistor 6T or eight-transistor 8T SRAM cells in a logic process to accommodate the processor, Venray is moving the processor to commodity-DRAM processes, whose 1T memory cells are cheaper to manufacture and less leaky.
Venray's Aurora test chip. Block diagram of Venray's "Shirtbook" tablet. The new Atom EC series previously known as Stellarton is suitable for some low-volume embedded applications that need to wrap an x86 processor in application-specific logic.
For one, Fusion processors for desktop PCs aren't ready yet. Wait until next year. Second, the new processors aren't only for netbooks. If OEM customers want to use these low-power processors to build large-screen notebooks or even desktop PCs, AMD is happy to sell them the chips, no strings attached.
And third, despite the hype over smartphones and tablets, netbooks remain a profitable market segment in which AMD has no presence whatsoever. AMD Fusion block diagram. AMD's first Fusion processors.
Target applications include small-business routers, network-attached storage NAS controllers, digital-video surveillance systems, and industrial control-area networks.
Today, Cavium announced four new series in the bit Octeon II family, populating a product line that now spans an unprecedented range from 1 to 32 CPU cores per chip. The new brood fills the low-end to midrange Octeon II line, leaving no significant gaps.
Cavium's Octeon II family. Key parameters for Cavium's Octeon II family. Comparison of midrange networking processors. Comparison of low-end networking processors. Now, Altera is again using embedded CPUs as bait to lure the industry toward reconfigurable logic.
These choices span a broader range of implementation options than ever before. Developers will be able to choose a hard core the foundry builds the CPU in fixed logic on the same die as the programmable fabric, soft cores developers compile a synthesizable CPU for the fabric at design time, and the Intel multichip module which pairs an Atom processor with an Altera FPGA.
The licensable K is a fully synthesizable core, is portable to any foundry, and is available now. MIPS32 K pipeline diagram. Within a few years, the Chinese hope, an all-native machine will rule the Top list of the world's biggest iron.
Three new Godson chips are in development. Godson-3C will be the fastest new member of the family, as well as the most sophisticated Chinese microprocessor yet disclosed.
A third new chip, Godson-2H, is a smaller single-core design with integrated GPU, memory controller, and peripheral controllers. Intended for low-cost PCs, netbooks, and embedded systems, Godson-2H will also be manufactured in 65nm and is slated for production in 2H Milestones of Godson evolution.
Godson GSV block diagram. Extending DPAA to the lower-priced chips allows software developers to use the same code, tools, drivers, frameworks, and application programming interfaces APIs across the whole QorIQ family.
New processors in Freescale's QorIQ family. Atom has almost totally eclipsed Via Technologies' Centaur processors, which pioneered the concept of a smaller and simpler x Athlon Neo runs much hotter than Atom, and AMD's other x86 processors are optimized for high performance in servers, desktops, and mainstream notebooks.
Now, AMD is clawing back. Its newest CPU core, code-named Bobcat, should beat Atom in single-thread performance at similar subwatt power levels. AMD Bobcat block diagram.
Its new Opteron server processors are intended for cloud-computing data centers that buy servers by the truckload. Although they can't match Xeon's most power-efficient models, they offer a less expensive alternative while still going easy on the electricity.
In all, AMD has introduced nine new Opteron processors. AMD Opteron and Opteron block diagrams. Key parameters for AMD's new series server processors. Comparison of low-priced versions of Opteron and Xeon.
Nine new chips are scheduled to sample this fall, each with the four-way multithreading and four-issue superscalar features of the previously announced eight-core XLP The new chips have one, two, four, or eight CPUs.
At the high end of the family, the previously announced eight-core XLP will be joined by another eight-core chip, the XLP These two chips, which are designed for network infrastructure, scale from 10Gbps to Gbps.
Multithreading and superscalar execution in NetLogic's EC NetLogic XLP block diagram. NetLogic's interchip interface ICI. Free link to this article PDF: Tier Logic has operational samples of its first programmable-logic chips and has already taken orders from early customers.
The company had planned to begin production by the end of this quarter. New Networking Chips Will Exceed 2. Although Freescale will continue making bit processors for years to come, its new P5-series chips in the QorIQ family will introduce a bit Power Architecture core, which is capable of multigigahertz clock speeds.
Freescale Semiconductor's QorIQ family. Called Gusto, it's licensed as process-portable intellectual property IP. It's large enough to store boot code and system firmware, rather than just code patches, configuration code, and trim settings for analog components.
In addition, Kilopass claims Gusto reads memory two to four times faster, cuts active power consumption by an order of magnitude, and slashes current leakage in standby mode by a factor of Two-transistor antifuse bit cell.
Antifuse bit-cell circuit diagrams. Electron micrograph of a Kilopass 2T antifuse bit cell at 40nm. XPM versus Gusto area comparison. Integration comparison of two hypothetical smartphones. Comparison of nonvolatile-memory NVM technologies.
Intel Adapts Larrabee for HPC [Brief Item] Intel's troubled manycore-processor project is steering away from discrete 3D graphics in favor of high-performance computing HPC, mainly for scientific and engineering applications.
It's a wise maneuver that will salvage Intel's investment in the Larrabee project, and the new direction is better suited to Intel's experience and expertise. But it won't avoid a collision with Nvidia, which is surging into the same market.
The xbased family of GPUs code-named Larrabee will spawn a new family of manycore processors code-named Knights. Both Larrabee and Knights can integrate dozens of x86 processor cores on a single chip.
The platform is intended for high-end smartphones, tablet computers, and the handheld computing devices that Intel formerly called mobile Internet devices, or MIDs. It will compete with processors designed for trendy products like the Apple iPhone, Nexus One, and Nokia N, but probably not with more-integrated processors designed for mainstream smartphones, like the Blackberry Bold and Blackberry Curve.
Menlow versus Moorestown integration. Die-photo comparison of Lincroft versus Silverthorne. Thermal images of Lincroft in two different power states. Forecast of smartphone processor shipments from to Power states for systems built with Intel's Moorestown chip set.
Estimated battery life of a Moorestown smartphone. Comparison of Intel's Moorestown with leading smartphone processors from Texas Instruments and Qualcomm. Moorestown Goes Embedded Sidebar: Decoding Intel's Code Names Editorial: Smartphone Spectrum Disorder Broadcast television in America, once described as a vast wasteland, now looks more like prime real estate.
Or rather, the radio-frequency spectrum that broadcast TV occupies is the suddenly valuable property. So valuable that some people in the telecommunications industry want to seize all that RF spectrum for wireless telephony and banish terrestrial TV broadcasting to the dustbin of history.
However, the real issue isn't the alleged obsolescence of broadcast TV. The wireless telcos and handset vendors are painting a marvelous vision of the future in which everyone carries a wireless device that delivers a dazzling array of features and services.
Unfortunately, there isn't enough spectrum available to make the vision come true. To differentiate its products and justify their higher prices, Apple must do more than wrap trend-setting industrial design and slick system software around other suppliers' standard parts.
By developing custom SoCs and embedded-processor cores, Apple is assuming more risk, but the potential payoffs are great: Now, Apple is absorbing Intrinsity, a small Austin-based company that sells embedded-processor cores, circuit-design tools, design services, and innovative intellectual property.
It's based on a 1. ARM Cortex-M4 block diagram. With these devices, the third spatial dimension exists for only a split-second slice of time. Tabula's devices can completely reconfigure their fabrics up to 1.
That's about one million times faster than conventional FPGAs. Rapid reconfiguration makes the physical fabric seem much larger than it really is. Tabula's first-generation chips can reuse the same physical gates for as many as eight different functions.
By rapidly reconfiguring the fabric, each physical gate can perform up to eight different functions. Tabula uses time to emulate the third spatial dimension, making one fabric seem like eight fabrics stacked together.
Each configuration is called a "fold" because it folds time into space. Tabula uses transparent latches as "time vias" to pass signals forward in time from one fold fabric configuration to another.
In a Tabula chip, time isn't linear. It's an endless loop, because the last fold wraps around to the first fold. The virtual stack is really a torus. Tabula's first-generation devices run at 1.
As chip-fabrication technology improves, Tabula's 3PLDs may derive greater benefits from Moore's law. Faster clock speeds allow Tabula to add more folds to its virtual 3D fabric.
This has implications for interconnects, as well as for gate density. Although Tabula's chips use single-ported SRAM instead of dual-ported SRAM for user memory, different function blocks can independently access the same memory during each fold.
Physical layout of logic tiles in a Tabula 3PLD. Ellen Clements It is with great sadness that we report the passing of our longtime colleague, Ellen Clements. Few readers of Microprocessor Report are familiar with Ellen, because her name didn't appear in the newsletter.
Yet, for 17 years, Ellen was one of the people who worked behind the scenes to ensure its quality. As far as anyone can remember, Ellen was the only copy editor in the year history of Microprocessor Report.
She began editing the newsletter in, six years after it was founded by Michael Slater in As a freelance contractor, Ellen edited every article for grammar, spelling, and style.
She also maintained our in-house style guide. Ellen had a long career in Silicon Valley as an editor, ghost writer, editorial consultant, and industry analyst. She entered the field in as an analyst for Dataquest, covering minicomputers and printers.
In addition to copy editing for Microprocessor Report, she worked with many other clients. Her academic background was eclectic. She did graduate work in sociology, anthropology, and linguistics at New York University, followed by additional study in German at the University of Vienna.
Ellen was an extrovert, an excellent conversationalist, a dreamer, and a romantic in the European sense. She loved opera and Shakespeare. Ellen's passing was sudden and unexpected.
She was working until her last day. In-Stat and the staff of Microprocessor Report offer our condolences to her family and especially to her surviving son and daughter, Duncan and Amanda.
Ellen, we will miss you. In late January, hundreds of customers, industry analysts, and reporters gathered at Oracle's headquarters in Redwood Shores, California, to hear Oracle and former Sun executives describe their plans for the merged company.
To be sure, the presentations were glossy and often lacked detail. However, the following messages were clear: Sun will not be drastically downsized in a quest for quick profits; Oracle is reinvesting in Sun's key product lines, including SPARC, Solaris, and Java; and Sun's hardware completes Oracle's evolution into a vertically integrated enterprise-technology company, much like IBM in the s.
Oracle didn't acquire Sun solely for the software, as some observers speculated. Of course, chip designers can use any processor cores for this purpose, but only a few cores have the built-in features, coherency control, and coherent debugging that make SMP easier to implement.
All these cores are licensable bit embedded processors supporting two-, three-, or four-way SMP with coherent memory systems. Top speed exceeds 2. This is one of the most complex bit embedded-processor cores yet seen.
All these bit licensable embedded-processor cores are designed for coherent symmetric multiprocessing. The trend of replacing 8- and bit microcontrollers with faster bit devices has processor vendors rushing to shrink their cores to tinier dimensions.
The smaller the core, the smaller the compromise in power consumption and cost when developers leave their 8- and bit chips behind. The latest entry in this race is the ARC Two closely related microarchitectures form the basis of the ARC microprocessor product line.
Sure, artificial environments are beguiling, whether they are created for videogames World of Warcraft, virtual worlds Second Life, Hollywood blockbusters Avatar, or professional training flight simulators.
But now, virtual reality is looking like a stepping stone toward a grander concept: Augmented reality combines some features of virtual reality with actual reality. It can overlay a live view of the real world with computer-generated graphics or textual information, building an enhanced version of reality that's easier to interpret or navigate.
Sometimes, augmented reality fabricates astonishing illusions that are entertaining as well as informative. Eventually, actual reality may come to seem drab, confusing, even dangerous. Google Goggles can identify books and paintings photographed with an Android smartphone camera.
Google Goggles can identify places of interest in live video images captured with an Android smartphone. Since the s, AMD and Intel have been marketing their microprocessors directly to consumers, using strategies that resemble the mass marketing of automobiles, fast food, laundry detergent, and other consumer products.
But it wasn't always that way. In the s, the idea seemed as silly as marketing capacitors to the general public. The transition of microprocessors from anonymous electronic components to consumer products is a fascinating study that was the subject of a recent discussion panel at the Computer History Museum in Silicon Valley.
But it's not just a history lesson. The coming collision between ARM and Intel in smartphones could be the force that brings PC-style microprocessor marketing to this new frontier.
A discussion about microprocessor marketing at the Computer History Museum brought together five panelists: Claude Leglise was Intel's marketing manager for all x86 processors from the to the Melissa Rey was a marketing communications manager at Intel who promoted all the x86 processors from the to the Dave House, a former Intel senior vice president, helped run Intel's microprocessor business from to Jack Browne was the marketing manager for Motorola's high-end microprocessors from to In addition to having new features, they are generally smaller and faster than their predecessors and use less power when fabricated in the same CMOS process.
The Xtensa 8 core is the smallest base configuration of Tensilica's Xtensa architecture and is intended primarily for bit microcontrollers. The Xtensa LX3 is much more configurable than Xtensa 8 and is intended primarily for data-plane processing and signal processing.
Tensilica's DSP product line. New asynchronous bus bridge for the Xtensa LX3. Tensilica Xtensa LX3 block diagram. Performance comparison, Xtensa LX3 vs.
Tensilica's Xtensa LX3 performance estimates, assuming two different fabrication processes, core configurations, and design flows. M14K processor flash-memory accelerator.
In a single-core configuration, it's small enough for workhorse microcontrollers, but a four-horse team of them can haul much bigger loads. Although it's smaller and slower than the Cortex-A8 or Cortex-A9 MPCore, it supports coherent multiprocessing with up to four cores, as well as uniprocessor configurations.
ARM Cortex-A5 block diagram. ARM Cortex-A5 trial layout. ARM Cortex-A5 quad-core block diagram. Fermi processors will continue to shoulder the graphics workloads in PCs, but they are taking the largest step yet toward becoming equal-partner coprocessors with CPUs.
JournallyMe iPhone App Demo. HTC One M9 vs. Say Note iPhone App Demo. The Apple keynote in 11 minutes. Apple iPhone 6 Review. Apple iPhone 6 Space Gray Unboxing. The video content is inappropriate.
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There was a problem filtering reviews right now. Please try again later. I've bought this Iphone as an brand new Apple. It comes looking like a brand new product. From the box to the device appearence, the charger and the headphones, But it has been not been an "Apple" experience at all.
I've had five Iphone before. Whith less than six months of light use, it started to seriously bug. I took it to an authorized premiun Apple technical assistance and just find out the phone was not original inside.
Apple cant even help me. They cant even fix it. The screen is not original and many other itens are from used phones. I do immediately request a position from the Amazon and from the seller.
This is seriuos fraud. Wait for your asnwer as soon as possible, before i take other providences. Comment people found this helpful. Was this review helpful to you? The guys from unlocked world have attach an other label with gb but the phone is 64gb!
So be very careful when you pick up your order they may have made mistake or intentionally make it like that I will not take anything from them anymore! The phone works excellent!!!
But is 64gb and I pay for gb!!!! Opened the box and there was play doh instead of a phone!! Comment 1, people found this helpful. I spect my money back NOW!!! I was fraud until today the box was open and my surprise is that in the interior theres no phone buy only a clay.
Si this a fraud o what need an answer. Read this if you are thinking of switching from Android!!! So I made the switch from using Android to the iPhone back in October, and I've been using the iPhone 6 for the past few months now and can give a detailed review on what it's like to switch over.
Before this switch, I've used the Samsung Galaxy S2 first smartphone ever! Here are my thoughts: Things that the iPhone does really well both hardware and software-wise: The behind the scene software for digitally capturing an image is definitely the strongest sell for the iPhone.
Other than the S5 and Note 4, no smartphone really comes close to having the same kind of image quality no matter the megapixels compared to the iPhone. This was one of the reasons for me to switch over since I've started to dabble with photography and wanted a really good camera in my smartphone.
Side note, if you read a lot of tech blogs, there is a notion that in the near future our smartphones won't accurately describe our devices anymore since making a phone call is probably one of the least commonly used features on a smartphone when you look at any average user.
Cameras, social media, emails all take a higher usage rate than making a call There have been maybe 2 or 3 times when my phone crashed and would have to be restarted, mostly due to playing some game that was not written very well for the iOS devices.
On Android devices, I've experienced a lot more crashes, and that may be due to the fact that so many apps haven't figured out the best way to optimize the app for each individual phone due to the fragmentation problems or something else.
Either way, I feel like the iOS environment and hardware is more reliable in my everyday use. Once you've used it, you won't go back. The S5 is not that close yet in terms of usability with their sensor.
The one in the iPhone 6 works really well. I definitely have found myself using my phone more because of how easy it is to unlock and install apps. This is an interesting point.
In general, you get way more control over how to use and how to integrate your apps on Android than iOS. But in iOS, it's really interesting that you can control the kind of notification that gets sent to your phone, background refresh, location requirement, and access to certain things like photos and camera.
In Android, you can do all of this as well, but sometimes for a lot of apps you have to have root access. Double tap to bring down the row of apps. I can't believe no one has thought of this before.
A lot of Android phones have gigantic screens, but no one has really figured out how to best get the users to interact with that. You can tap the home button twice on the iPhone to bring down the top few rows of the apps so that you can access them in one hand use.
Here are the things that I miss on Android: Full integration of almost any apps and control of default apps. I can set default apps on Android whereas Apple does not allow that. I can open up photos and upload them to Dropbox or any other app that I choose to, whereas Apple doesn't allow uploading to Dropbox via the Photos app you have to open up Dropbox, then select upload and then go to Photos from there.
In the mail app for Android, you can attach almost any file on the phone. You can't do that on Apple. You can't even attach a single file. You have to share a file as an email.
So, forget about replying an email with an attachment. This is pretty annoying. Productivity is better on Android. If you are a big dropbox user, you probably know and love Dropsync on Android seriously, best 5 bucks spent on any app.
You can have an app that syncs and download any material from Dropbox onto your Android and then sync it back up when changes are detected. Apple does NOT allow that mainly because they don't allow background apps from accessing the hard drive, or something along those lines.
So you have to download the file you are interested in manually from the Dropbox app. It just slows you down a lot, especially if you get to a part of a building where there is weak signal for wifi or cellular data.
Notifications are way better. Why can't Apple make one button that clears all of your notifications? You have to individually close each app's own notification. I pretty much leave my notification screen untouched.
Some other things that many already know: Material design looks awesome! Way better widgets and the fact that you can have widgets!! Oh, and you can swipe right on the home screen on Android and that brings another screen from the left side More customization and etc.
Overall, I think the iPhone is a fine device to use and you probably won't regret investing in one. The customer service from Apple is top notch, even if their parts cost an arm and leg.
I think that, and I hate to say this because it's going to sound like every blog writer out there, the choice really does come down to personal preference and what you use the phone for. So, I've broken down my recommendation based on user case scenarios: If you are user type The integration with all the apps and the feature with dropbox is just so important to anyone who works on their phones and other mobile devices.
I would either get a pure Google device N5 or N6, I like smaller phones Samsung and HTC are also good choices but updates may be slow. One Plus One is actually pretty cool. They are not the best when it comes to customer service since they're a small company filling huge demand, but from my experience, the device is solid and definitely a work horse.
Medical and Science community: Unfortunately, most of the med and science people rely on Apple products, and a lot of new apps still come to iOS first or are better updated and designed on iOS.
Recreational, use a phone as a communication device and for fun: The camera and social apps are fun to use on the iPhone. This is a split.
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